This invention relates to a semiconductor device provided with a protection circuit, and more particularly to a construction of the protection circuit which protects a semiconductor element such as a MOS field effect transistor (hereinafter referred to as a MOS FET) from a high voltage applied abruptly thereto.
A semiconductor integrated circuit (hereinafter referred to as an IC) is apt to be damaged by an abnormally high voltage applied thereto. In particular, an IC having MOS FETs as circuit elements can be easily destroyed by a surge voltage due to resulting high levels of electrostatic charges. For preventing such damage, various protection circuits have been proposed. These conventional protection circuits were generally constructed with a resistor and a switch such as a transistor which turns on in response to a voltage higher than a predetermined voltage.
One such conventional protection circuit is shown in FIG. 1, and will be explained hereunder with reference to FIGS. 1, 2 and 3. MOS FET's Q.sub.2 and Q.sub.3 constitute an inverter as an input stage of a circuit formed on a semiconductor chip. The source electrode of the MOS FET Q.sub.2 is grounded at a ground terminal. The drain electrode of the MOS FET Q.sub.3 is connected to a power supply terminal V.sub.DD. The source electrode of the MOS FET Q.sub.3 and the drain electrode of the MOS FET Q.sub.2 are connected to each other to supply a signal obtained at the connection point 4 to the following circuit (not shown) formed on the same semiconductor chip. Between an input terminal 1 and the gate electrode 2 of the MOS FET Q.sub.2, a resistor R.sub.1 formed by an impurity diffusion is inserted. A diode D.sub.1 and a protection transistor Q.sub.1 are connected between the gate electrode 2 of the MOS FET Q.sub.2 and the ground terminal 3. The protection transistor Q.sub.1 is an NPN type bipolar transistor having a collector connected to the gate electrode 2 of the MOS FET Q.sub.2, an emitter grounded at the ground terminal 3 and a base connected to the ground terminal 3 through a resistor R.sub.2.
This protection circuit is realized on a semiconductor substrate 11 as shown in FIGS. 2 and 3. An N.sup.+ region 12 operating as the resistor R.sub.1, and N.sup.+ regions 15 and 16 operating respectively as the collector and the emitter of the protection transistor Q.sub.1 are formed in the P-type semiconductor substrate 11. The N.sup.+ region 16 is connected to the ground terminal 3 (not shown in FIGS. 2 and 3) through an Al wiring layer 21. The N.sup.+ region 15 and a contact region 14 provided at one end of the N.sup.+ region 12 are commonly connected to an Al wiring layer 20 to make connection to the gate electrode of the MOS FET Q.sub.2 (not shown in FIGS. 2 and 3). A contact region 13 provided at the other end of the N.sup.+ region 12 is connected to the input terminal 1 (not shown in FIGS. 2 and 3) with an Al wiring layer 19. The substrate 11 is grounded by way of a metal layer 17 formed on its back surface. The wiring layers 19, 20 and 21 are disposed on a field insulator film 18 formed on the substrate 11 and connected with the N.sup.+ regions 12, 15 and 16 through windows of the field insulator film 18. It should be noted that the resistor R.sub.2 in FIG. 1 is an effective resistance component of a portion of the substrate 11 operating as the base of the protection transistor Q.sub.1 and that the diode D.sub.1 is formed by a PN-junction between the N.sup.+ region 15 and the substrate 11.
The resistor R.sub.1, the diode D.sub.1, the protection transistor Q.sub.1 and the resistor R.sub.2 constitute a protection circuit for protecting the MOS FET Q.sub.2, especially for protecting the gate insulator film of the MOS FET Q.sub.2, from an abnormally high voltage which is accidentally or unexpectedly applied to the input terminal 1. When a high positive voltage is applied to the input terminal 1, the PN-junction between the N.sup.+ region 15 and the substrate 11 is broken down, causing injection of electrons into the substrate 11. Due to this injection, the potential of the substrate between the N.sup.+ regions 15 and 16 rises due to the resistance component R.sub.2 to bias forwardly the PN-junction between the N.sup.+ regions 16 and the substrate 11. As a result, a lateral type NPN transistor (Q.sub.1) formed by the N.sup.+ regions 15 and 16 and the portion of the substrate therebetween turns on, forming a current path from the N.sup.+ region 15 to the ground through the substrate 11, the N.sup.+ region 16 and the wiring layer 21. This current path lowers the voltage at the gate electrode of the MOS FET Q.sub.2, resulting in protection of the MOS FET Q.sub.2.
On the other hand, when a high negative voltage is applied to the input terminal 1, the PN-junction of the N.sup.+ region 12 and the substrate 11 is forwardly biased. Consequently, the diode D.sub.1 turns on, forming a current path through the PN-junction. The presence of this current path also lowers the voltage at the gate electrode of the MOS FET Q.sub.2. In this way, if either a positive or a negative high voltage is applied to the input terminal 1, the protection circuit protects the MOS FET Q.sub.2.
As IC technology has advanced, however, the integration density and the operation speed semiconductor devices has been improved. These improvements have been realized by minimizing the size of MOS FET's. As a result, recent types of MOS FET's have become more sensitive to an applied voltage and require more effective protection circuits.
The conventional protection circuit uses a discrete transistor as the protection transistor Q.sub.1. Such a discrete transistor has a comparatively small current capacity. If an input having a large voltage is applied to the input terminal 1, the protection transistor may be thermally destroyed by excessive current, or the voltage rise at the collector may cause damage the MOS FET Q.sub.2.
Various improvements of the protection circuit have been proposed. In one proposed improvement, the resistance of the resistor R.sub.1 is increased. A The large resistance, however, makes the operation speed of the circuit in an IC slow. This is because the operation speed of the MOS FET Q.sub.2 is determined by RC time constant of the protection circuit. Therefore, the best solution in the prior art has been a compromise between protecting against excessive input voltages and the operation speed of the IC, i.e., between increasing the size of the protection transistor Q.sub.1 and the increased resistance of the resistor R.sub.1. This is not a completely satisfactory solution since a large area for is required the protection circuit, resulting in an overall reduction of integration density.